The present invention relates to a digital information processing integrated circuit (IC), and more particularly to a digital information processing IC for detecting a delay between interfacing clocks and setting initial data loading/unloading parameters of the IC automatically.
FIG. 1 is a schematic block diagram illustrating a clocked system having a master circuit 10 such as a microprocessor, e.g., CPU, and a slave circuit 20 such as a semiconductor memory device and a signal bus (or system bus). Referring to FIG. 1, the slave circuit 20 is externally interfaced with the master circuit 10 through clock and data paths. The master circuit 10 generates a clock signal CLK_OUT and data DATA_OUT which are intended for the slave circuit 20. The slave circuit 20 receives the clock signal CLK_OUT and the data DATA_OUT, and then generates a clock signal CLK_IN and data DATA_IN for the master circuit 10. The clock signal CLK_IN is a feedback clock signal of the output clock signal CLK_OUT. The master circuit 10 uses the clock signal CLK_IN in loading the data DATA_IN from the slave circuit 20, and processes the loaded input data DATA_IN internally with the clock signal CLK_OUT.
FIGS. 2A-2C are timing diagrams illustrating a relationship between input and output clock signals CLK_IN and CLK_OUT of the master circuit of FIG. 1. Referring to FIGS. 2A-2C, there exists a delay between the clock signals CLK_OUT and CLK_IN caused by the structure of the motherboard, which includes the master circuit 10 and slave circuit 20.
In prior systems, the delay did not cause a substantial problem because of the relatively low clock speed of the circuits. As shown in FIG. 2A, the low clock speed ensures a sufficient operating margin for data loading and unloading operations of the master circuit 10. Recent improvements in technology have caused the clock speed of the master circuit 10 and the slave circuit 20 to increase. As shown in FIG. 2B, as the clock speed of the circuits 10 and 20 increases, the operating margin is reduced. As a result, the data DATA_IN from the slave circuit 20 can be transmitted to the master circuit 10 with undesirable faults. To illustrate, referring to FIG. 2C, if the clock speed is so high so as not to ensure the operating margin, it is difficult to transmit the data DATA_IN to the master circuit without error. The data unloading process of the master circuit 10 cannot be performed after the data loading operation, since the output clock signal CLK_OUT occurs prior to the input clock signal CLK_IN, without the operating margin. In particular, in a high-performance computer system, avoiding this interfacing problem becomes more difficult as processing speed increases. One solution of the problem is a clock forwarding method.
FIG. 3 is a timing diagram illustrating a relationship between input and output clock signals CLK_IN and CLK_OUT of the master circuit 10 of FIG. 1 in which a clock forwarding method is applied. In this method, several clock periods corresponding to the delay are forwarded to the output clock signal CLK_OUT by a clock forwarding circuit 100 of FIG. 1. Thus, the data unloading process of the master circuit 10 can be performed after the data loading operation. Therefore, the input data DATA_IN from the slave circuit 20 can is transmitted to the master circuit 10 without error.
Initial data loading/unloading parameters of the clock forwarding circuit 100 must be determined. Generally, the initial parameters are predetermined and stored manually in an external read only memory (ROM) (not shown) coupled to the clock forwarding circuit 100 as a fixed value by a motherboard designer. In initializing the master circuit 10 after powering up, the initial parameters are loaded to the clock forwarding circuit 100 such that clocks can be forwarded. As shown in FIG. 3, by forwarding clocks, the loaded input data from the slave circuit 20 can be unloaded to the master circuit 10 in faultless fashion.
Examples of the clock forwarding method are illustrated in U.S. Pat. No. 4,811,364 to Sager et al., issued on Mar. 7, 1989, xe2x80x9cMETHOD AND APPARATUS FOR STABILIZED DATA TRANSMISSIONxe2x80x9d; U.S. Pat. No. 4,979,190 to Sager et al., issued on Dec. 18, 1990, xe2x80x9cMETHOD AND APPARATUS FOR STABILIZED DATA TRANSMISSIONxe2x80x9d; and U.S. Pat. No. 4,525,849 to Wolf, issued on Jun. 25, 1985, xe2x80x9cDATA TRANSMISSION FACILITY BETWEEN TWO ASYNCHRONOUSLY CONTROLLED DATA PROCESSING SYSTEMS WITH A BUFFER MEMORYxe2x80x9d, all of whose discloses are incorporated herein by reference.
As described above, in prior conventional systems, the initial parameters for forwarding clocks are provided manually by a motherboard designer, so that product cost is increased in proportion to the increased labor. In addition, since the initial parameters are stored to the external ROM as fixed values, undesirable faults of data transmission can occur due to product deviation. For these reasons, it is difficult to stabilize data transmission between clocked circuits.
It is therefore an object of the present invention to provide a digital information processing IC for automatically detecting a delay between interfacing clocks and setting initial data loading/unloading parameters to stabilize data transmission between clocked circuits.
In order to attain the above objects, according to an aspect of the present invention, there is provided a digital system comprising a master circuit having a clock forwarding circuit for generating a first clock signal and a slave circuit coupled to the master circuit for generating a second clock signal synchronized with the first clock signal. The clock forwarding circuit receives the second clock signal, detects a delay between the first and second clock signals, and sets initial data load/unload parameters of the master circuit based on the detected delay.
In one aspect, the clock forwarding circuit of the invention includes a clock generator for generating a clock signal and a data control logic coupled to the clock generator and an internal data bus, the data control logic outputting data to a slave circuit in response to the clock signal. An output clock control logic is coupled to the clock generator to provide the clock signal to the slave circuit as an output clock signal by controlling the clock signal. A delay detection circuit detects a delay between the output clock signal and an input clock signal and generates an initial parameter for forwarding clocks corresponding to the detected delay. The input clock signal is a feedback clock signal of the output clock signal. A load/unload clock control logic is coupled to the delay detection circuit and the input clock control logic to generate load control signals and unload control signals in response to the initial parameter. An input clock control logic is coupled between the clock generator and the load/unload clock control logic to provide the clock signal from the clock generator to the load/unload clock control logic by controlling the clock signal. A load/unload multiplexer loads input data from the slave circuit and unloads the loaded input data to the internal data bus of the master circuit via the data control logic in response to the load and unload control signals from the load/unload clock control logic.
As is apparent from the foregoing, according to the digital system of the invention, data transmission between clocked circuits can be performed without error independently of the delay.